Achronix is launching a groundbreaking FPGA family of products to improve performance with flexibility for high bandwidth data acceleration applications

Achronix Semiconductor Corporation, the leader in field programmable gate array (FPGA) -based hardware acceleration devices and high-performance embedded FPGA(eFPGA) Semiconductor intellectual property (IP), today announced the creation of an innovative, new FPGA family of products to meet the growing demand for artificial intelligence/machine learning (AI/ML) and high-bandwidth data-accelerated applications.Achronix Speedster 7t series is based on a highly optimized new architecture that goes well beyond traditional FPGA solutions with asic-like performance, simplified design, and enhanced FPGA flexibility.

Speedster7t FPGA series is designed for high bandwidth applications with a revolutionary new 2D on-chip network (2D NoC) and a new high-density machine learning processor (MLP) module array.By combining the programmability of the FPGA with ASIC's wiring structure and computing engine, Speedster7t creates a new class of "FPGA +" technology.

As the application scenarios of artificial intelligence/machine learning evolve rapidly, new solutions are required to cope with different requirements in terms of high performance, flexibility and time-to-market.The FPGA market for artificial intelligence applications is expected to triple to $5.2 billion over the next four years, according to Semico Research.

"We are in the early stages of a high-growth phase of intelligent, self-learning computing that will broadly impact our everyday lives."Robert Blake, President and CEO of Achronix Semiconductor, said: "Speedster7t is the most exciting release in the history of Achronix and represents the legacy of innovation and software development built on four generations of architecture and close collaboration with our leading customers.Speedster7t is the combination of flexible FPGA technology with ASIC core efficiency, thus providing a new category of 'FPGA+' chips that can significantly increase the limits of high-performance technology."

In FPGA development Speedster7t series products in the process, the Achronix completely rethink the whole FPGA architecture engineering team, to balance sheet processing, interconnection and external input/output interface (I/O), in order to maximize throughput of data intensive applications, these scenarios visible at those based on edge and AI/ML application based on the server, network processing and storage.

Speedster7t devices are manufactured using TSMC's 7nm FinFET process and are specifically designed to receive large amounts of data from multiple high-speed sources, while also distributing that data to the programmable chip's algorithmic and processing units, which then provide those results with the lowest possible latency.The Speedster7t family includes interfaces such as the high bandwidth GDDR6 interface, the 400G Ethernet port, and the PCI Express Gen5 interface, all of which are interconnected to provide asic-level bandwidth while retaining the full programmability of the FPGA.

"Achronix's new Speedster7t FPGA range is a remarkable example of the explosion of innovative chip architectures designed to process massive amounts of data directly into AI applications," said Rich Wawrzyniak, chief market analyst for ASIC and SoC at Semico Research."By integrating mathematical functions, memory, and programmability into its machine learning processors, combined with cross-chip, two-dimensional NoC architecture, this is an excellent way to eliminate bottlenecks and ensure the free flow of data throughout the device.In AI/ML applications, memory bandwidth is everything, and Achronix Speedster7t provides impressive performance metrics in this area.

Highly optimized for computational performance

At the heart of the Speedster7t FPGA is its new machine learning processor (MLP), a large-scale parallel array of programmable cells that provide the highest fpga-based computing density in the industry.MLP is a highly configurable, computation-intensive unit module that supports 4-24 bit integral formats and efficient floating point patterns, including 16-bit support for TensorFlow and direct support for supercharged block floating point formats that doubles the computing engine of each MLP.

MLPS are closely adjacent to embedded memory modules, ensuring maximum performance of 750 MHz for data transfer to MLPS by eliminating the delays associated with FPGA wiring in traditional designs.This combination of high-density computing and high-performance data transfer enables processor logic arrays to provide fpga-based maximum available computing power in teraflops (TOPS, Tera-Operations Per Second).

World class bandwidth

The key to high performance computing and machine learning systems is the high off-chip memory bandwidth that provides storage sources and buffers for multiple data streams.Speedster7t devices are the only FPGA to support GDDR6 memory, which is the external storage device with the highest bandwidth.Each GDDR6 storage controller can support 512 Gbps of bandwidth. Speedster7t devices have up to 8 GDDR6 controllers that can support 4 Tbps of GDDR6 cumulative bandwidth and provide the equivalent storage bandwidth of hbm-based FPGA at a very small cost.

"Micron is pleased to partner with Achronix to deliver the world's first FPGA product that directly loads GDDR6 for high-bandwidth storage needs," said Mal Humphrey, vice President of marketing for meron's computing and networking business."Innovative and scalable solutions like these will drive differentiation in the field of artificial intelligence, where heterogeneous computing alternatives and high-performance storage are an essential part of accelerating the acquisition of data content."

In addition to this exceptional storage bandwidth, Speedster7t devices include the industry's highest performance interface ports to support extremely high bandwidth data streams.Speedster7t devices boast up to 72 of the industry's highest performance SerDes, capable of speeds ranging from 1 to 112 Gbps.There are also 400G Ethernet MAC hardware with forward error correction (FEC), configurations that support 4x 100G and 8x 50G, and a hardware PCI Express Gen5 controller with 8 or 16 channels per controller.

Ultra-efficient data movement

From Speedster7t high-speed I/O port and memory of tens of thousands of megabit data easily swamped the traditional logic array FPGA programmable interconnection for bits of routing capabilities, and Speedster7t structure contains a across and vertical cross the FPGA logic array of innovative, high bandwidth of two-dimensional slices on network (NOC), they are connected to all the FPGA high-speed data interface and memory.They are like the air highway network superimposed on top of the FPGA interconnect city street system, Speedster7t's NoC support chips to handle the high-bandwidth communications required between engines.Each row or column in the NoC can be implemented as two 256-bit, one-way, industry-standard AXI channels with a working frequency of 2Ghz, and can provide 512 Gbps of data flow for each direction.

The implementation of a dedicated 2d NoC in Speedster greatly simplifies high-speed data movement and ensures that data streams can be easily directed to any custom processing engine within the entire FPGA architecture.Most importantly, NOC eliminates the congestion and performance bottlenecks that traditional FPGA USES programmable routing and logical lookup table resources to move data flows throughout the FPGA.This high-performance network not only increases Speedster7t FPGA's total bandwidth capacity, but also increases effective LUT capacity while reducing power consumption.

Security features for security first and hardware assurance applications

Speedster7t FPGA series products are available in the face of the threat of third-party attacks, the most advanced bitstream security protection features, they have a multi-layer defense ability to protect the confidentiality and integrity of bitstream.The key is encrypted based on tamper-proof physical non-cloning technology (PUF), and the bitstream is encrypted and verified by a 256-bit aes-gcm encryption algorithm.To prevent attacks from side channels, the bitstream is segmented, each data segment USES a separate exported key, and the decryption hardware USES a differential power analysis (DPA) counter measure.In addition, the 2048-bit RSA public key authentication protocol is used to enable decryption and authentication hardware.Users can be assured that when they load their secure bitstream, it is the expected configuration because it has been authenticated with the RSA public key, the aes-gcm private key, and the CRC check.

Proven ways to convert to low-cost asics to meet high-volume demand

Achronix is the only company that offers both standalone FPGA chips and Speedcore?Embedded FPGA(eFPGA) semiconductor intellectual property rights (IP) company.Achronix USES the same technology used in Speedcore eFPGA IP as in Speedster7t FPGA to support seamless conversion from Speedster7t FPGA to ASIC.FPGA applications usually have functions that must remain programmable, while other fixed functions are specific to specific system applications.For ASIC conversion, fixed functions can be solidified into ASIC structures, thereby reducing chip size, cost, and power consumption.When Speedcore eFPGA IP is used to convert Speedster7t FPGA to ASIC, customers are expected to save up to 50% in power consumption and 90% in cost.

supply

Speedster7t FPGA devices range in size from 363K to 2.6M for a 6 input lookup table (LUT).ACE design tools that support all Achronix products are now available, including Speedcore eFPGA and Speedchip FPGA chiplets.

The first batch of components and development boards for evaluation will be available in the fourth quarter of 2019.