Microchip entered the memory infrastructure market to launch the industry's first commercial serial memory controller

SMC 1000 8 x 25G supports the high memory bandwidth required for next-generation cpus and SoC for ai and machine learning.

Traditional parallel DRAM memory has become a major obstacle to the next generation of cpus, as artificial intelligence (AI) and machine learning workloads increasingly require more computing power and require more memory channels to provide more memory bandwidth.Microchip Technology inc. today announced its entry into the memory infrastructure market, introducing the industry's first commercial serial memory controller and expanding its data center portfolio.SMC 1000 8 x 25G enables cpus and other computation-centric socs to use quad memory channels connected in parallel to DDR4 DRAM within the same package size.Microchip's serial memory controller not only provides higher memory bandwidth and media independence for computation-intensive platforms, but also has the characteristics of ultra-low time delay.

As the number of CPU processing cores increases, the average memory bandwidth available for each processing kernel decreases because the CPU and SoC devices cannot extend the number of parallel DDR interfaces on a single chip to meet the increasing number of cores.The SMC 1000 8 x 25G is connected to the CPU through the 25 Gbps channel that conforms to the 8-bit open memory interface (OMI) and to the memory through the 72-bit DDR4 3200 interface, thereby significantly reducing the number of host CPU or SoC pins required for each DDR4 memory channel, allowing more memory channels and increasing available memory bandwidth.

A CPU or SoC that supports OMI can use a large number of media types with different cost, power, and performance metrics without having to integrate a separate memory controller for each type.In contrast, the current CPU and SoC memory interfaces are typically locked to specific DDR interface protocols at specific interface rates, such as DDR4.SMC 1000 8 x 25G is the first Microchip memory infrastructure product to support the media independent OMI interface.

Data center application workloads require an OMI based DDIMM storage product to provide the same high performance bandwidth and low latency as today's parallel ddr-based storage products.The SMC 1000 8 x 25G of Microchip USES an innovative low delay design that adds less than 4 ns of delay to the traditional integrated lrdim-based DDR controller, indicating that the bandwidth and delay performance of the OMI based DDIMM product is almost identical to similar LRDIMM products.

Pete Hazen, Microchip vice President of data center solutions, said, "Microchip is pleased to introduce the industry's first serial memory controller product to the market.New memory interface technologies, such as the open memory interface (OMI), enable a large number of SoC applications to support the growing storage needs of high-performance data center applications.Microchip's entry into the memory infrastructure market underscores our commitment to improve data center performance and efficiency."

Steve Fields, chief architect of IBM Power Systems, said: "IBM customers' workloads were so demanding of storage that we made a strategic decision about the Power processor memory interface to use the OMI standard interface to increase storage bandwidth.IBM is pleased to partner with Microchip to launch this solution."

SMART Modular, Micron and samsung electronics are developing multiple high-efficiency 84-pin differential dual-row DDIMM, which ranges in capacity from 16gb to 256gb and fits the JEDEC DDR5 draft DDIMM package.These DDIMM will be SMC 1000 8 x 25G and will seamlessly connect to any 25 Gbps OMI interface.

"The open storage interface (OMI) standard provides a highly pin efficient serial storage interface, so a large number of CPU and SoC applications can extend storage bandwidth and seamlessly convert between an increasing number of emerging media types, such as storage hierarchical storage," said Myron Slota, President of the OpenCAPI consortium.The OpenCAPI alliance provides host and target ips free of charge and will simultaneously initiate a series of measures to ensure compliance with the standards."

"Google customers can benefit from data-intensive applications, such as machine learning and data analytics that require high-performance memory," said Rob Sprinkle, head of platform infrastructure technology at Google LLC.Google strongly supports open standards-based initiatives such as the open storage interface (OMI), which can provide high-performance storage interfaces to meet important performance goals such as bandwidth and latency."

The development tools

To support customer development of OMI compliant systems, SMC 1000 is equipped with design software and ChipLink diagnostic tools that provide a range of debugging, diagnostic, configuration and analysis tools through an intuitive GUI.