FPGA chip cooling design

For any chip to work, it must satisfy a temperature range, which refers to the temperature on the silicon wafer, commonly referred to as junction temperature.

FPGA of ALTERA is divided into commercial grade and industrial grade. The junction temperature range for normal operation of commercial grade chips is 0~85 c, while that of industrial grade chips is -40~100 c.In practical circuits, we must ensure that the junction temperature of the chip is within the tolerable range.

As the power consumption of the chip increases, more and more heat will be generated during operation.If the junction temperature of the chip is to be maintained within the normal range, certain methods must be adopted to make the heat generated by the chip rapidly disperse into the environment.

Had learned the person of middle school physics to know, heat transfer basically USES 3 kinds of methods, namely conduction, convection and radiate, chip is to use these kinds of means to heat radiate outwards likewise.

The following figure shows a simplified model of chip cooling.Heat generated by the chip in the figure is mainly transmitted to the outer package of the chip. If there is no attached heat sink, it will be directly distributed to the environment by the chip package shell.If a heat sink is added, the heat will be transferred from the outer package of the chip to the heat sink through the heat sink adhesive, and then from the heat sink to the environment.Generally speaking, the surface area of the fin is quite large, and the contact surface with the air is large, which is conducive to heat transfer.In daily practice, it has been found that most of the heat sinks are black, because black objects tend to radiate heat outward, which is also conducive to heat emission outward.And the faster the wind speed on the fin surface, the better the heat dissipation.

In addition, a small amount of heat passes through the substrate of the chip to the solder ball of the chip, which then passes through the PCB to transfer the heat to the environment.Due to the small proportion of heat, this part is ignored in the following discussion of the thermal resistance of chip packaging and heat sink.

First of all, it is necessary to understand the concept of "thermal resistance", which describes the ability of an object to conduct heat. The smaller the thermal resistance is, the better the thermal conductivity is, and vice versa, which is similar to the concept of resistance.

From the silicon chip of the chip to the thermal resistance of the environment, assuming that all the heat is eventually distributed to the environment by the heat sink, a simple thermal resistance model can be obtained, as shown in the figure below:

                                                                                                                                                       Chip cooling model with heat sink

The total thermal resistance from the silicon wafer to the environment is called JA, so it satisfies the following requirements:

JA = JC + CS + SA

JC refers to the thermal resistance of the chip to the outer package, which is generally provided by the chip supplier.CS refers to the thermal resistance of the outer package of the chip to the heat sink. If the heat sink is attached to the chip surface with heat conducting adhesive, the thermal resistance is the thermal resistance of the hot glue, which is generally provided by the heat conducting adhesive supplier.SA refers to the thermal resistance of the heat sink to the environment, which is generally given by the heat sink manufacturer. The thermal resistance decreases with the increase of wind speed, and the manufacturer usually gives the thermal resistance under different wind speeds.

Chip packaging itself is as a cooling device.If there is no heat sink in the chip, JA refers to the thermal resistance value of the silicon chip after external packaging, which is obviously higher than the JA value of the heat sink.This value depends on the characteristics of the chip itself and is typically supplied by the chip manufacturer.

The graphic below shows the package thermal resistance of ALTERA's STRATIX IV devices.JA values of chips under various wind speeds are given, and these values can be used to calculate the situation without radiators.In addition, JC is used to calculate the total JA value with heat sink.

StraTIx iv device packages heat resistance

Assuming that the power consumed by the silicon wafer is P, then:

TJ (junction temperature) =TA+P*JA

It is necessary to satisfy that TJ cannot exceed the maximum allowable junction temperature of the chip, and then the maximum allowable requirement for JA can be calculated according to the ambient temperature and the actual power consumed by the chip.

JAMax= (tjmax-ta) /P TA (ambient temperature)

If the JA value of the chip package itself is greater than this value, it must be considered to add appropriate cooling devices to the chip to reduce the effective JA value of the chip to the environment and prevent the chip from overheating.

In the actual system, part of the heat will also be released from the PCB, if the PCB layer number, larger area, is also very conducive to heat dissipation.