Dedicated AI speeds up the contradiction between computation force and power consumption

According to the reporter's observation, most AI chips on the market today are indeed equipped with dedicated hardware acceleration modules, especially AI image processing and visual recognition.From kirin series chips used by huawei in the early stage of smartphones, A11 and A12 by apple, Xavier used by Nvidia in the automotive field, and numerous types of asics emerging in the market today, dedicated AI accelerator seems to have become a standard configuration for professional support of image and visual data processing for specific applications.This has also led to a market phenomenon, as today's chips without AI accelerators may not be easy to claim as AI chips, let alone to deal with customers with such products.

Special AI configuration of the accelerator, the purpose is to cater to the current each segment application scenario for the different needs of AI, focus on AI chip research and development of a start-up company controller tells a reporter: "just like today's smart phones, users may for smart image photographed and AI optimization of this kind of demand is more, so the chip vendors will specially designed corresponding accelerator to run a particular image and visual algorithm, the results of the output can be meet users' expectations, this is the current many vendors competing product advantage is very important;In addition, in the automotive field, the demand may be different. The on-board camera needs to collect a large amount of image data all the time, which will have higher requirements in terms of chip bandwidth, delay and power consumption (after all, it is the car standard).Once the parameters of the model get larger and larger, in fact, there is no way for the system to continue to save all the parameters in the chip, which will inevitably become the bottleneck, which is exactly the value of designing special AI accelerator.

From the perspective of AI accelerator architecture itself, almost all AI accelerators today have a computing unit responsible for completing matrix multiplication/convolution operations in deep learning, such as pulse array or dot multiplier represented by TPU.And another on-chip storage unit, which is mainly responsible for storing the input/output and weight of each layer."This design approach of heterogeneous coprocessor can be very flexible in performance. On the one hand, it can use pipeline and parallel structure to keep up with algorithm updates and performance requirements.On the other hand, it can provide broadband, low-latency interfaces for the main processor and system memory, increase the amount of computation performed by SoC and optimize data structure, reduce the demand for bandwidth, and improve chip performance by hundreds of times while reducing power consumption."Added the head of an AI chip start-up.

Of course, the configuration of dedicated AI acceleration modules has a great help to improve the overall performance of chips in fixed application scenarios, and can reduce the contradiction between computing force and power consumption to a large extent.However, there are advantages and disadvantages. Due to the limited application scenarios supported by this scheme, the scalability and flexibility of the chip on the application side are further lost.And AI evolution speed is faster and faster, if the future more and more popular AI algorithms, neural network gradually fade into the background, so the chip side will need to be specifically for the acceleration of new kinds of algorithms to do special module design, it will further enhance the cost and development time of the chip, hard to catch up with the vagaries of AI application market.Therefore, there are different views in the industry on whether the AI accelerator mode will become the mainstream way of AI chip design in the future.

"Now manufacturers are doing AI accelerators, essentially for demand.Because the demand is different, so in the demand has not been the industry to reach a high degree of consensus, the chip is bound to be very different.Simply put, for example, in some AI visual image applications, the chip is not too sensitive to front-end power consumption, and some very complex operations are required, which may not be well solved by using a typical terminal AI chip.However, on the other hand, in some applications, it will have a very lightweight operation.In short, I don't think it's going to be an ip-like business model when there's no clear commercial need."

Standing in the point of view of a AI chip start-up, the reporter understands, as many chips of entrepreneurial teams would rather go now develop AI accelerator route to do their own special ASIC, is also due to some very bullish on segment market, the market is worth their investment of time and effort to develop the corresponding AI accelerated chip solutions.Because it's almost impossible for such companies to compete in the general-purpose chip market with the likes of nvidia and Intel, it's better to pick a few niches to do business in.Market segments generally have the characteristics of low competition, high demand concentration, very clear, so many requirements, relatively standard, it is very suitable to use special AI accelerator to build SoC mode to do.

On the other hand, while chip giants such as qualcomm, nvidia and Intel are focused on the larger traditional applications, such as servers in the cloud, and the marginal markets, such as mobile phones and cars, where the user base is strong.This can be seen from a series of product releases in recent years by the three major players of AI accelerator chips, such as Tesla V100 and Xavier of nvidia.Hexagon DSP and cv-isp's AI Engine in qualcomm snapdragon 855, and the recently released Cloud AI 100;Intel's low power Movidius accelerator and the latest Cascade Lake Xeon.

That doesn't mean the chip giants aren't interested in niche-sized markets such as IoT, where the likes of Intel, ST, and renesas are starting to make inroad, according to our reporters.Last November, for example, Intel released two AI accelerator solutions for smart cities, retail and health care: the Intel Movidius processor array, the Intel Arria10 FPGA;ST also launched a DNN accelerator based on stm32cubemx.ai at the STM32 summit on April 26-27 this year.In the same month, renesas electronics' configurable AI accelerator, DRP, was released, further enhancing the MCU's chip computing power with e-ai.Presumably in the future a period of time, there will be more chip industry giants rush, then AI accelerator market is bound to usher in an unprecedented battle, for those deep subdivision of the small and medium-sized chip manufacturers is undoubtedly a great challenge.

In short, no matter how the market situation changes, what the application side needs from beginning to end is an AI chip with high computing power and low power consumption, and this feature will be paid more attention by the market with the gradual integration of AI and IoT applications.Therefore, for the current large or small AI chip design manufacturers, how to solve the contradiction between chip computing power and power consumption through the optimization of hardware and algorithm end is the key, which may require manufacturers to study in many aspects and multiple angles, such as chip manufacturing process, architecture and cost.AI accelerator is able to solve the contradictory between power consumption and is the most direct and effective solution, but according to the reporter, now a lot of strong AI chip giants have begun to layout and into the market, and aiming at all kinds of scenarios to launch both suitability strong AI accelerator chips, it must be for the current lots of trying to "struggle with" chip in the emerging market segment of AI players very big impact.Therefore, there is little time left for such companies. How to flexibly rely on localization and their expertise in professional fields to accelerate the opening of various market segments and win more customers will be the key for these emerging AI chip players to survive in the next few years.